// Copyright (C) 1953-2020 NUDT
// Verilog module name - host_output_schedule 
// Version: HQM_V1.0
// Created:
//         by - fenglin 
//         at - 10.2020
////////////////////////////////////////////////////////////////////////////
// Description:
//         cache bufid of not ts packet with fifo.
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module host_output_schedule
(
        i_clk          ,
        i_rst_n        ,
                       
        iv_desp_network       ,
        i_desp_wr_network     ,
		
		iv_desp_host          ,
		i_desp_wr_host        ,
		o_desp_ack_host       ,
		
        ov_bufid       ,
        o_bufid_wr     ,
        i_bufid_ready
);

// I/O
// clk & rst
input                  i_clk;
input                  i_rst_n;  
//tsntag & bufid input from host_port
input          [11:0]  iv_desp_network;
input                  i_desp_wr_network;

input          [11:0]  iv_desp_host    ;
input                  i_desp_wr_host  ;
output                 o_desp_ack_host ;
//tsntag & bufid output
output         [8:0]   ov_bufid;
output                 o_bufid_wr;
input                  i_bufid_ready;

wire           [8:0]   wv_fifo_wdata;
wire                   w_fifo_wr;
wire                   w_fifo_empty;
wire                   w_fifo_rd;
wire           [8:0]   wv_fifo_rdata;
(*MARK_DEBUG="true"*)wire           [3:0]   wv_data_count;
(*MARK_DEBUG="true"*)wire                   w_full;
host_input_queue host_input_queue_inst(
.i_clk              (i_clk   ),
.i_rst_n            (i_rst_n ),

.iv_bufid_network   (iv_desp_network[8:0]   ),
.i_bufid_wr_network (i_desp_wr_network      ),

.iv_desp_host       (iv_desp_host[8:0]   ),
.i_desp_wr_host     (i_desp_wr_host      ),
.o_desp_ack_host    (o_desp_ack_host     ),

.ov_fifo_wdata(wv_fifo_wdata),
.o_fifo_wr(w_fifo_wr)
);
//xilinx ip
/*
syncfifo_showahead_aclr_w9d16 syncfifo_showahead_aclr_w9d16_inst(
    .din  (wv_fifo_wdata  ), 
    .wr_en (w_fifo_wr),
    .rd_en (w_fifo_rd),
    .clk   (i_clk),
    .srst   (!i_rst_n), 
    .dout  (wv_fifo_rdata),    
    .data_count (wv_data_count),
    .full  (w_full), 
    .empty (w_fifo_empty) 
);
*/
//altera ip

syncfifo_showahead_aclr_w9d16 syncfifo_showahead_aclr_w9d16_inst(
    .data  (wv_fifo_wdata  ), 
    .wrreq (w_fifo_wr),
    .rdreq (w_fifo_rd),
    .clock (i_clk),
    .aclr  (!i_rst_n), 
    .q     (wv_fifo_rdata),    
    .usedw (wv_data_count),
    .full  (w_full), 
    .empty (w_fifo_empty) 
);

host_output_queue host_output_queue_inst(
.i_clk        (i_clk  ),
.i_rst_n      (i_rst_n),

.i_fifo_empty (w_fifo_empty),
.o_fifo_rd    (w_fifo_rd),
.iv_fifo_rdata(wv_fifo_rdata),

.ov_bufid     (ov_bufid),
.o_bufid_wr   (o_bufid_wr),
.i_bufid_ready(i_bufid_ready)
);
endmodule